1. Field of the Invention
This invention relates to the field of television receivers having processors for high definition video signals, for example MPEG 2 format signals, and in particular, to television receivers that convert between high definition video formats.
2. Description of Related Art
The following description uses certain abbreviations and designations related to video signal identification and/or video signal formats. These high definition formats have been defined by the ATSC. The term 720p refers to a video signal having 720 lines of video in each progressive (non-interlaced) frame. The term 1080i refers to a video signal having 1,080 interlaced horizontal lines in top and bottom fields, each field having 540 horizontal lines. In accordance with this convention, the term 720i would denote 720 lines of interlaced video per frame and the term 1080p would denote 1,080 lines of progressive horizontal lines in each frame.
In some situations an arriving 720p signal is to be ultimately displayed on a 720p display, but is first converted to 1080i for transmission to the display processor. The 1080i is first deinterlaced and is then passed through a reverse conversion calculation to reconstitute the original 720p signal with no additional vertical resolution loss or aliasing produced on non-moving scenes. Some high definition MPEG decoders will convert all incoming ATSC signals into 1080i format. This is not desirable for a 720p display.
If a 720p ATSC signal is received by a television receiver having a 720p display, such a signal can ordinarily be displayed optimally only in its original format. Unfortunately, some high-definition MPEG decoders are only designed to output a 1080i signal for HDTV, regardless of the format of the video source supplied to the MPEG decoder. Thus, a need exists for converting a received progressive signal from a decoded interlaced signal back to a progressive signal for optimal display.
In a first aspect of the present invention, a method of optimizing the display of an up-converted interlaced video frame signal from a received progressive video frame signal comprises the steps of receiving a progressive video frame signal, decoding the progressive video frame signal using an interpolation function to provide an interpolated interlaced video signal, deinterlacing the interpolated interlaced video signal, and de-interpolating the deinterlaced interpolated interlaced video signal to provide an optimized progressive video frame signal.
In a second aspect of the present invention, a video receiver device optimized to enable the display of an upconverted interlaced video frame signal from a received progressive video frame signal comprises a video receiver and a video processor coupled to the video receiver, wherein the video processor comprises a high definition video decoder having an interpolator, a deinterlacer, and a reverse interpolator.
In a third aspect of the present invention, a video receiver device optimized to display an up-converted interlaced video frame signal from a received progressive video frame signal comprises a video receiver and a processor coupled to the video receiver. Preferably, the processor is programmed to receive the received progressive video frame signal, decode the received progressive video frame signal using an interpolation function to provide an interpolated interlaced video signal, deinterlace the interpolated interlaced video signal, and de-interpolate the deinterlaced interpolated interlaced video signal to provide an optimized progressive video frame signal.